1. Field of the Invention
The present invention relates to a semiconductor memory device and to a method of controlling a semiconductor memory device and, more particularly, to a semiconductor memory device using a DRAM memory core which requires high-speed processing and a method of controlling the same.
2. Description of the Related Art
In recent years, a burst operation has often been used for fast access to a semiconductor memory device (memory). A burst operation is intended to execute data input/output from and to the outside at high speed. In the burst operation, an address given when a read or write command is given from the outside is set as an initial value and after that, subsequent necessary addresses are internally generated and are synchronized with an external signal (clock signal: CLK). For example, a synchronous DRAM (SDRAM) has such a function. In a known semiconductor memory device, a read/write signal (CL) to output data from a memory core after sense-amplification is generated from “CLK”. “CL” is used to activate the sense amplifier to read data from the memory core in case of a read operation (READ), and is used to write data to the memory core in case of a write operation (WRITE).
Moreover, for example, in case of a pseudo static RAM (SRAM) interface, a refresh operation (REF) is carried out in intervals of READ or WRITE. In case of a semiconductor memory device in which a burst operation with an unlimited burst length (BL) is possible, a row address can be changed during the burst operation and this requires a change of a word line.
The REF and the changing of the word line can interfere with a periodical read/write signal request (CL request) from “CLK”. If the REF and the changing operation of the word line have a priority, a recovery time and a cycle performance is sacrificed and this decreases the performance of the semiconductor memory device.
Regarding a prior memory having a burst mode, a memory was suggested in which a mask control of a data bus for processing is carried out in response to a mask signal which requires a prohibition of a predetermined write operation whereby high-speed reading is made possible (for example, refer to Japanese Unexamined patent Publication (Kokai) No. 11-283385).
Moreover, conventionally, a memory device has been proposed in which a write amplifier control circuit activates a write amplifier when writing according to a command, and inactivates the write amplifier in response to a data mask signal when writing, and a column decoder control circuit controls an activation of a column decoder so that the column decoder is not activated in response to the data mask signal (for example, refer to Japanese Unexamined Patent Publication (Kokai) No. 2000-113671).
Furthermore, a semiconductor integrated circuit has been proposed in which an internal circuit starts an operation on receiving an address signal before fetching a command signal and an address changing circuit inhibits a transmission of the address signal to the internal circuit on receiving an internal command signal or a clock signal in order to enable a high-speed operation and allow a decrease in power consumption (for example, refer to Japanese Unexamined Patent Publication (Kokai) No. 2001-167576).
The prior art and its associated problems will be described in detail later with reference to accompanying drawings.